Design verification is a common process for testing a newly designed integrated circuit board, or system-level architecture, to confirm that it complies with the requirements defined by the specification of the architecture for that device. Design verification for a device under test (DUT) may be performed on the actual device, but usually a simulation model of the device is tested.
There are typically two main types of design verification methods: dynamic verification (also known as “experimental verification” or “test verification”), which tests the DUT by providing inputs to the DUT (typically via a testbench) and checking outputs from the DUT, and formal verification, which analyses the DUT to determine its correctness. The two most popular methods for automatic formal verification are language containment and model checking.
Constrained random verification may involve choosing a suitable hardware verification language (HVL), defining a testbench architecture and producing constraints to be used for generating proper (legal) random stimuli. When the testbench is used in simulating a DUT, a random seed value and a simulator may become part of the verification environment. The seed may help in reproducing a failure (bug) if the other inputs (e.g., the testbench architecture—components hierarchy and the set of constraints used) remain constant. Any change to these inputs may lead to different results despite using the same seed value. The random seed value and the constraints may be fed or provided to a constraint solver which is typically, in many cases, an integrated part of the simulator, to generate random values.